Occasional Contributor
Regular ContributorHi,
Just would like to follow up with you on this. Thank you.
Occasional ContributorHi,
Thanks again so much for your support and help. I just tested my design on signal tab logic analyzer. I noticed that the data sequence is perfectly fine. I have also emailed you the design files together with signal tab logic analyzer file so that you can also have a look. The transciever signals like rx_syncstatus and rx_pattern detect are also working fine. Now I am confident that my HDL design is all working fine.
But I still have issues with printing of inconsistent data on UART output terminal. I have the feeling that to display my data on UART terminal, I need to make a whole soc_system which requires to incorporate HPS into the design. Now I utilised Qsys tool in Quartus software to connect my HDL design with HPS. Now my transceiver's pll clock is 62.5MHz. I am running Linux on my HPS. So that means the Linux application that I wrote for the HPS to print my transceiver received parallel data onto the UART terminal is running on much lower clock than that of my transceiver's pll clock. Is it possible to involve an UART terminal expert who can help us in this issue?
