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New Contributor

4 months ago

How to customize the Agilex 7 I-series OS build with SOF and HPS changes ?

Hi Team, So we are working with Agilex 7 I-series Evaluation kit, We have successfully built yocto image for the GSRD as explained in this guide : https://altera-fpga.github.io/rel-24.3.1/embedded...

tehjingy_Altera

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Regular Contributor

4 months ago

Hi

Did you managed to go through the materials shared?

Do you have any follow-up questions?

Regards

Jingyang, Teh

sujan19
New Contributor
4 months ago
Hi,

Yes i went through the resource, looking fine till now.

As u previously mentioned that the dts file is in : https://github.com/altera-fpga/linux-socfpga/tree/socfpga-6.12.11-lts/arch/arm64/boot/dts/intel
Which file to be exact, from the resource it seems that its this :
linux-socfpga/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb
But this is compiled dtb, where is the source of this dtb, And this is only for PS side, if I'm not wrong.

Where is the one for pl for ex: In Xilinx FPGA's its pl.dtsi & system-user.dtsi (for PL to PS conf).
Can you let me know the intel equivalent of these dts ?
Regards,
Sujan
- sujan19
  New Contributor
  4 months ago
  Hi,
  
  I found this guide for FPGA to HPS bridges for linux : https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/f-series/soc/setup-use-bridges/ug-setup-use-bridges-agx7f-soc/
  
  Shouldn't we follow this procedure not the linux boot examples, when our design contain Bridges like msgDMA , pio & interrupts ?
  
  Regards,
  Sujan