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CJere3
New Contributor
New Contributorhow to access f2h sdram through hps
在使用hps调用tse ip核中，根据https://rocketboards.org/foswiki/Projects/AlteraSoCTripleSpeedEthernetDesignExample的tse示例工程。通过两个scatter-Gather DMA（master）与HPS中的f2h sdram（slave）进行tse的数据通信。 问题是：我如何通过上位机直接访问这...
FawazJ_Altera
Frequent Contributor
Frequent ContributorHello,
This is done through the SDRAM controller subsystem. each controller is connected to a DDR. Only one f2sdram bridge is sufficient.
As shown in the design I sent to you earlier. you can connect Avalon master on FPGA to Address Span extender IP. Inside this IP, you can define the starting region of your SDRAM which assigned to FPGA. This is configurable option.
in the example above, the address span extender looks at this sdram with base address of 0x20000000, so anything below this address is not seen by FPGA.
Thanks
