how to access f2h sdram through hps

Hello,

This is done through the SDRAM controller subsystem. each controller is connected to a DDR. Only one f2sdram bridge is sufficient.

As shown in the design I sent to you earlier. you can connect Avalon master on FPGA to Address Span extender IP. Inside this IP, you can define the starting region of your SDRAM which assigned to FPGA. This is configurable option.

in the example above, the address span extender looks at this sdram with base address of 0x20000000, so anything below this address is not seen by FPGA.

Thanks