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hasssanadeli's avatar
hasssanadeli
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3 years ago

FPGA clock frequency

Hello, To program the FPGA of MitySom-5CSX, I was wondering if could anyone tell me the FPGA clock frequency pin number and its value. I tried 50MHz and AA8 pin number but it did not work. Thanks,
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Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


What do you mean it did not work? How did you set the clock frequency and how did you check for it?


Regards,

Nurina


hasssanadeli's avatar
hasssanadeli
Icon for New Contributor rankNew Contributor
3 years ago

Hello Nurina,

Thanks for your response. We are using MATLAB HDL coder to generate VHDL codes and synthesis and analysis of FPGA. In one step in the target platform, we need to assign the clock frequency port and its value. When I run it I face this error:

" Error (175019): Illegal constraint of I/O pad to the location PIN_AA8
Info (14596): Information about the failing component(s):
Info (175028): The I/O pad name(s): CLKIN
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (169094): Can't place pin CLKIN at location AA8 (PAD_50) because that location is a dedicated programming pin location (1 location affected) File: PIN_AA8"

Thanks,

Hassan

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago
    Hi,
    where did you get the idea to use pin AA8 as clock input? I presume your board has a user manual telling which pins are wired to a clock source to be used as FPGA clock. If not, there's a Cyclone V pinout file, also Quartus pin planner gives the information. I checked pinout file and found that AA8 is configuration DCLK, surely not suited as FPGA clock input.
    • hasssanadeli's avatar
      hasssanadeli
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi, thanks for your response I checked the datasheet but unlike the other FPGA devices I used before this controller is more complicated and I could not exactly find out which pin is related to the FPGA clock.