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Chloé_Russell's avatar
Chloé_Russell
Icon for New Contributor rankNew Contributor
7 years ago

EPCQL controller I Quartus version 16.0

Hello, I am trying to access in read and write my EPCQL-1024 from simple soft running in NIOSII. I have the Altera Serial Flash Controller I configured in QUAD mode connected from its avl_csr and a...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Chloe, JTAG is the bridge to enable communication between Host PC and FPGA. Correct frequency is needed in order to establish a clean and correct timing waveform for JTAG signals. This is probably the reason that you don’t see any effect after you have performed write operation / erase operation. Once you have re-powered the board, the communication will become normal and you are able to see the action that you have done previously (erase sector or write specific data to specific address). Thank You. Regards, YL