Forum Discussion
YuanLi_S_Intel
Regular Contributor
7 years agoHi Chloe,
JTAG is the bridge to enable communication between Host PC and FPGA. Correct frequency is needed in order to establish a clean and correct timing waveform for JTAG signals. This is probably the reason that you don’t see any effect after you have performed write operation / erase operation. Once you have re-powered the board, the communication will become normal and you are able to see the action that you have done previously (erase sector or write specific data to specific address).
Thank You.
Regards,
YL
- Chloé_Russell7 years ago
New Contributor
Hi, I’ve posted a question about FD support, I did not get any reply and I’m confused a little bit using the drivers (I do not know when to use functions with File Descriptor support, does using file descriptor support need to work with Linux?). Your reply will be much appreciated. Here is my question : This is my first use of Software drivers. I'm working with the Quartus standard version 16.0. when I used the "altera_avalon_uart_write" and "altera_avalon_uart_read" functions, things go right.. but when trying to use FD (altera_avalon_uart_write_fd and altera_avalon_uart_read_fd) , the parameter SP points to a false base address although the file has been correctly opened, it returns a valid value (!=NULL). my code is : int main() { altera_avalon_uart_state* sp_UART_0; altera_avalon_uart_state* sp_UART_1; sp_UART_0->base = UART_0_BASE; sp_UART_1->base = UART_1_BASE; char tx_buffer[8] = "BITBANG"; char rx_buffer[8]; alt_fd* fp_uart_1; alt_fd* fp_uart_0; fp_uart_1= open ("/dev/uart_1", O_RDWR); //Open file for reading and writing fp_uart_0= open ("/dev/uart_0",O_RDWR); //Open file for reading and writing printf("call init uart\n"); altera_avalon_uart_init(sp_UART_1, UART_1_IRQ_INTERRUPT_CONTROLLER_ID,UART_1_IRQ); altera_avalon_uart_init(sp_UART_0, UART_0_IRQ_INTERRUPT_CONTROLLER_ID,UART_0_IRQ); int wr = altera_avalon_uart_write_fd (fp_uart_1,tx_buffer,sizeof(tx_buffer)) ; printf("wr = %d\n",wr); alt_busy_sleep(1000000); / delay 1us /// 1 s int rd = altera_avalon_uart_read_fd (fp_uart_0,rx_buffer,sizeof(tx_buffer)) ; alt_busy_sleep(1000000); / delay 1us /// 1 s printf(" rd = %d\n",rd); printf("rx_buffer = '%s'\n\n",rx_buffer); printf("sp_UART_0 base = 0x%08X \n", sp_UART_0->base); printf("sp_UART_0 ctrl = 0x%08X \n", sp_UART_0->ctrl); printf("sp_UART_0 tx_buf = '%s' \n", sp_UART_0->tx_buf); printf("sp_UART_0 rx_buf = '%s' \n\n\n", sp_UART_0->rx_buf); printf("sp_UART_1 base = 0x%08X \n", sp_UART_1->base); printf("sp_UART_1 ctrl = 0x%08X \n", sp_UART_1->ctrl); printf("sp_UART_1 tx_buf = '%s' \n", sp_UART_1->tx_buf); printf("sp_UART_1 rx_buf = '%s' \n\n", sp_UART_1->rx_buf); printf(" rx_buffer = %s\n",rx_buffer); altera_avalon_uart_close (fp_uart_1) ; altera_avalon_uart_close (fp_uart_0) ; free(fp_uart_1); free(fp_uart_0); return 0; } Best regards, CR - Chloé_Russell7 years ago
New Contributor
Hi , I’ve generated .jic file of NIOSII system with debug module and my test is successfully running on board. When trying to remove debug module and with same steps (new .hex file to respond new configuration .sopcinfo and new .sof) I’ve generated a new .jic file for the system without debug module and after configuring my board nothing works. Thank you for helping me solving the problem by telling me if I’ve to add some option for the system without debug module. Best regards Chloe