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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
5 months ago
Solved

Custom board on Cyclone V HPS SDRAM preloader test

Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock...
Board Debug
  • BrianSune_Froum's avatar
    BrianSune_Froum
    4 months ago

    The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
    The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
    UBOOT memory normal test also passed w/o any errors.

    So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

    No matter it is /w or /wo the board settings no drop no crash no stuck.

    So the case ends here.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
5 months ago

Hi

Could you share a screenshot of all the DDR setting that you have currently made in the quartus project?

Regards

Jingyang, Teh

BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
5 months ago

Hi,

First allow me to rephase the layout.

it is used fly-by and byte pin are swapped. i.e. DQ0-DQ7 <-> HPS DQ0-DQ7 is allowed to interchange any pins.
DQ DQM DQS are routed length matched.
All address are strictly followed no pin exchange and length matched.

Based on the above design which works on ZYNQ 7000 series.

The Qsys:

Board settings are not modified as EVM/EVB from other company work normally during development on software side and PL side do not modify those parameter as well.