Zarquin
Occasional Contributor
Occasional ContributorC5SX Dev Kit RGII pinning fails
Dear community, on the C5SX development kit I would like to test a 1 GB Ethernet connection with the Triple Speed Ethernet IP core. The core is configured with an RGMII output to the Micrel KSZ9021...
I now think the problem with the pins on the CVSX SoC is because the RGMII pins are in the HPS (Hardware Processor System) part of the FPGA, which cannot be directly connected by FPGA vhdl code.
