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Rink's avatar
Rink
Icon for New Contributor rankNew Contributor
7 years ago

Accessing the Global Timer from the FPGA (Cyclone V SoC)?

Is it possible for the FPGA logic side to access the Global Timer?

Does it involve a memory-access via the FPGA–to–HPS bridge perhaps?

I am interested in capturing the value to resolve event timing across the FPGA and HPS boundaries?

Thanks!

1 Reply

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hello,

    Are you trying to access a register from HPS?

    You can access any register in HPS by FPGA master through f2h bridge.

    If you are trying to access a memory location, say for example your HPS will write a data to memory location, you can access this location by FPGA master through f2sdram bridge.

    Thanks