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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yet another PUF issue.

Hi all. I asked some PUF related questions on these boards before, and I am still looking for a good way to implement a PUF on the Altera FPGAs using Quartus II. So far I've tried: Race ba...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

So I tried implementing this on an Altera DE2 board. I used the 7seg display to output 32 bits. I used toggle switches to control the always-high "CLK" signal, and the "excite" signal.

The results across 3 different boards were different, but not 100% different. About half the hex digits were the identical between the boards. Between different inputs, the results were also different, but again, not 100%.

I'm not sure if this can be remedied.

I have a concern about the compilation and how the amount of logic cells used on each of the 32 sections (BPUFslice) of the BPUF seem to be different. As shown in the screenshot.

Is this normal? Would the results improve if an equal amount of cells were used to create each section?

Also, can I manually set where the sections are placed on the chip?

I included the project if you guys wanna take a look.

Thanks! :)

http://img128.imageshack.us/img128/5823/lcsay6.th.jpg (http://img128.imageshack.us/my.php?image=lcsay6.jpg)http://img128.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)