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Altera_Forum's avatar
Altera_Forum
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17 years ago

Yet another PUF issue.

Hi all. I asked some PUF related questions on these boards before, and I am still looking for a good way to implement a PUF on the Altera FPGAs using Quartus II. So far I've tried: Race ba...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The drawing in the paper, particularly the designatator clk is possibly misleading. With a DFF, as in your code, the circuit is completely stable. The unstable operation is achieved with a latch respectively a combinational loop. Most FPGA families don't have hardware latches of the shown kind, thus the circuit has to be formed by two logic cells.

If I understand right, the latch signal clk is always enabled and the clr signal is unused.