Forum Discussion

Zak's avatar
Zak
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Wrong resource usage for MAX V design

Hello, I'm performing a feasibility study for a custom project and I need to estimate the resource usage of a test design on a MAX V device: 5M160ZE64I5. I've never used MAX V, I've experience wi...
  • KennyT_altera's avatar
    KennyT_altera
    6 years ago

    Another possible situation that your design had been optimized away. You can look for the analysis report to get those information


KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Another possible situation that your design had been optimized away. You can look for the analysis report to get those information


  • Zak's avatar
    Zak
    Icon for New Contributor rankNew Contributor
    6 years ago

    Yes, that's just it! Since it is a test design some entity outputs weren't connected...

    The weird thing is also a PIO and an SPI Slave to Avalon Master IP cores are optimized away with no reason. Both IPs have I/Os connected to I/O pads and are linked together with an Avalon bus.

    Anyway, thanks to led me towards an explanation of this phenomenon.