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VinceP's avatar
VinceP
Icon for New Contributor rankNew Contributor
5 years ago

Wrong behavior in mixed-HDL simulation

Hi everyone, I'm struggling to solve an issue inside my Modelsim simulation. I have my testbench written in VHDL, which instantiates a component written in VHDL as well (the UUT), and a simulat...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Vincenzo,


You can use RTL viewer and Technology map to analyze and debug your design. You may have to check your RTL for intended function is correctly made or otherwise.


Thanks,

Regards