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Honored Contributor

8 years ago

Writing Fast State Machines using SystemVerilog

Hello, I came across this article that commented on using State Machines with One-Hot encoding. http://www.verilogpro.com/systemverilog-one-hot-state-machine/ The article state, "Ac...

Altera_Forum

Honored Contributor

8 years ago

For state machines with 3 or more states, it infers 1 hot by default. But you can force it to use counter or grey (or others) code using attributes or synthesis directives:

http://quartushelp.altera.com/15.0/mergedprojects/hdl/vlog/vlog_file_dir_syn_encoding.htm

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Writing Fast State Machines using SystemVerilog

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