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Honored Contributor
Honored ContributorWrite from FPGA to external processor's memory
Hi, I am creating a design that implements a counter (Qsys interval timer) in FPGA and to write these counter values to external processor's memory via PCIe. I memory mapped the counter to PCIe...
Altera_ForumHonored Contributor
Honored ContributorHi Dave,
I have created the Qsys design with Nios II processor connected to TXS port of PCIe hard ip to access the x86(host) processor DDR3 memory. In the previous posts you have mentioned that "The TXS port opens up a 1MB window (or whatever size you configured it to be) on the PCIe address map. Before you write to anywhere in that map, you need to have a driver on the host that allocates memory and then locks it, so that PCIe can access it". I want to know after the driver allocate a memory in the host processor, how x86(host) writes the address of the memory to the address translation table. Thanks in advance.
