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What would be the connection if I have DDR2, NIOSII, PCIE and SGDMA? Should NIOSII data master and instruction master be connected to PCIe txs or bar or cra?
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If you build a Qsys system containing these components, then all of these devices "sit" on the Avalon bus. The processor, PCIe, and DMA controller are all bus masters, so they can initiate transfers on the Avalon-MM bus. If you want to initiate a transfer on the PCIe bus, then an Avalon master (other than the PCIe master) can initiate a transfer to the txs end-point. The LSBs of the PCIe address are set by the Avalon address, while the MSBs are set by a register accessible by an Avalon master in the CRA area (so that address has to be written first). This unfortunately makes the SGDMA controller not-so-useful for performing PCIe DMA, since it can only generate 32-bit addresses (unless you also include DMA entries to have it re-write the CRA address MSBs).
Cheers,
Dave
Honored Contributor
