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Is host-processor considered to be Avalon-MM master in this case ?
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Draw yourself a picture or block diagram and things may become clearer.
* A NIOS processor inside the FPGA can be an Avalon-MM master
A PCIe bridge can contain both PCIe master (initiator) and slave (target), and internal to the FPGA can be both an Avalon-MM master or a slave.
If the NIOS processor or a DMA processor inside the FPGA was to write to PCIe memory on the host then you would have:
* NIOS/DMA Avalon-MM master -> PCIe bridge Avalon-MM slave interface -> PCIe master/initiator performs the PCIe transaction.
If the host processor was performing an access to an Avalon-MM slave, eg., a register inside the FPGA, then you would have:
* Host processor PCIe master -> PCIe bridge PCIe slave interface -> Avalon-MM master interface (part of the bridge) -> accesses the Avalon-MM slave register
Each time you go through a bridge from one protocol to another, you can modify the address.
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The PCIe should see the address space on the host processor in order to write to that reserved memory space. Can you tell me if PCIe to host processor address mapping is as per "PCI Express-to-Avalon-MM Address Translation" as mentioned in the Altera's PCIe guide ?
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"The PCIe" means what? Again, ask clear questions, and it'll make providing clear responses easier.
Here's what I think you are asking:
For the Altera PCIe-to-Avalon-MM bridge, what is the PCIe Initiator Address mapping?
Or another way, if I perform an Avalon-MM access to the TXS slave of the bridge, how does that translate to a PCIe address?
The answer is; the low address bits are taken from the Avalon-MM address, and the MSBs are set by a register in the bridge. The MSBs need to be set by your software, after the host allocates and locks some memory into the PCIe address map (as viewed by all the devices attached to the same PCIe bus your board is plugged into).
So what is going on, why is this needed? Consider the following; your board is plugged into a PCIe bus with a 64-bit address, and you are a 32-bit processor ... how can you "see" the 64-bit PCIe address map? The answer is, that you cannot, you can only see a small window into the PCIe address map. If your window was 32-bits, then you would be able to "see" 4GB of the PCIe address map, but you would have no space for any other Avalon-MM devices. The Qsys PCIe bridge allows you to create several small windows, eg., some windows with a default size of 1MB.
Take a look at this Qsys/PCIe thread. There's a document there that might help:
http://www.alteraforum.com/forum/showthread.php?t=35678 Cheers,
Dave
Honored Contributor
