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I am creating a design that implements a counter (Qsys interval timer) in FPGA and to write these counter values to external processor's memory via PCIe. I memory mapped the counter to PCIe BAR0. Next, I want to run this counter and keep writing to few location in processor's external memory.
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You are mixing terminology here - which leads me to believe you may not understand PCIe.
BAR0 is what the host processor uses to talk to a PCIe end-point, i.e., your Qsys design.
If your Qsys design is going to access the host (external processor) memory, then it would use the TXS interface. Before the Qsys system is allowed to use PCIe to write to the host memory, you would need to reserve host memory and then get its physical address, which would then be programmed into the TXS address translation register.
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How does the FPGA see the processor address map on PCIe so it knows where to write to ?
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The TXS port opens up a 1MB window (or whatever size you configured it to be) on the PCIe address map. Before you write to anywhere in that map, you need to have a driver on the host that allocates memory and then locks it, so that PCIe can access it.
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In order to make the above design work, I also need help with Qsys configuration and connections.
1. Should PCIe be configured as native endpoint or root port ?
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If your hardware is plugged into a PCIe slot, then it needs to be an end-point.
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2. I have only three connection between PCIe and counter: pcie-clk to counter-clk, pcie-reset to counter-reset and pcie-BAR0 to counter-slave. Do I need to connect any other PCIe ports to the counter (like cra, txs) ?
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You need an Avalon-MM master connected to TXS to perform the 'write' to PCIe. If you want your counter value written to PCIe, then you need to write an Avalon-MM master that generates a PCIe write each time the counter is updated. Alternatively you could just have a NIOS II processor read the counter and then write to PCIe.
Cheers,
Dave
Honored Contributor
