wire signed [10:-11]root3x_full; How do I implement this in VHDL?

You cannot do it directly, you'll have to offset it:

signal root3x_full : signed(10+11 downto 0);

Unless you used the fixed point libraries:

signal root3x_full : sfixed(10 downto -11);

You might be better off learning VHDL than just getting a forum to do it for you.