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Yes, that apparently doesn't work with recent Quartus versions. There's still an option to specify a std_logic_vector of maximum size, but not to use all bits. The unused bits will be ignored in synthesis, but you possibly get some warnings. I'm doing similar by using not fully populated arrays.
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Thanks, i was thinking of something like that before. This seems to be somehow a quck'n'dirty hack. I wonder how this works if you connect ports in a top level entity. For example if you have the fifo, and then you connect it to a 8 bit data bus, when the fifo's max length is 32 bit. This won't compile, right? Do yo have an example for that?
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