Will Quartus ever support Verilog hierarchical parameter referencing?

Imagine an addition module which decomposes the addition in different ways depending on width. Small widths are done in a single cycle but larger widths are recursively decomposed into smaller chunks which takes extra clock cycles. The calling module needs to know when the result will be ready. Hence the need to read an "attribute" of the addition module, in this case "pipeline delay". Ideally this would be read only, perhaps by using a localparam (this works fine in Modelsim assuming it is actually compliant with the Verilog LRM). Yes, this could be done dynamically with a flag but my system pipeline is all statically arranged/aligned at elaboration time, not run time.