Honored ContributorHi,
Attached is a snapshot of my Timing Report from TimeQuest. I noticed uTsu is negative, so when it is substracted from Data Required Path, it actually makes a positive contribution to the final data required time. How could that be? What is the meaning of a negative setup time?
Honored ContributorI've seen that before. The bottom line is that there's some fudging going on to account for something else. Note that the timing numbers aren't always black and white. For example, a path might be broken up into a register's uTco, an IC delay, a LUT delay, and the uTsu of the register. But the distinction between each point may not be so clear cut, and say, it would be easy to make the IC delay a little larger if the LUT delay was a little smaller, and vice versa. (I'm not saying numbers are being moved around for the heck of it, but that there's muxing/transistor logic between an IC delay and the LUT, and you can really count them on whatever side you want). By itself, it doesn't make a whole lot of sense, but I've received the response that it is correct.
Honored ContributorThank you:)
