Why QuartusII sysnthesis tool interpreting this verilog code as a latch?

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input  RxStreamData0;
reg  ReqInFifoDataIn;
always @(posedge AppClk or negedge PcieRstN)
  if (!PcieRstN) 
  begin 
    ReqInFifoDataIn    <= 96'b0;     ReqInFifoDataValid <= 1'b0; 
    ReqInFifoDataVal   <= 1'b0; 
  end 
  else 
  begin 
    ReqInFifoDataIn <= RxStreamData0; 
    ReqInFifoDataValid    <= RxStreamValid0; 
    ReqInFifoDataVal      <= ReqInFifoRd; 
  end 
  
 wire wTag;
 
 assign wTag = RxStreamData0 & ~ReqInFifoDataIn; 

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Hi,

the reason could be your reset initialization. You are trying to set 96 bit to "0", but your reg vector is only " reg [81:0] ReqInFifoDataIn;"

Kind regards

GPK