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Altera_Forum's avatar
Altera_Forum
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16 years ago

Why QuartusII sysnthesis tool interpreting this verilog code as a latch?

I have question about the verilog code causing Latch and not flip-flop. Your suggestions are welcome. I can add more register stage to this but that can affect the performance. I am not su...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

input  RxStreamData0;
reg  ReqInFifoDataIn;
always @(posedge AppClk or negedge PcieRstN)
  if (!PcieRstN) 
  begin 
    ReqInFifoDataIn    <= 96'b0; 
    ReqInFifoDataValid <= 1'b0; 
    ReqInFifoDataVal   <= 1'b0; 
  end 
  else 
  begin 
    ReqInFifoDataIn <= RxStreamData0; 
    ReqInFifoDataValid    <= RxStreamValid0; 
    ReqInFifoDataVal      <= ReqInFifoRd; 
  end 
  
 wire wTag;
 
 assign wTag = RxStreamData0 & ~ReqInFifoDataIn;