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Altera_Forum's avatar
Altera_Forum
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16 years ago

Why QuartusII sysnthesis tool interpreting this verilog code as a latch?

I have question about the verilog code causing Latch and not flip-flop. Your suggestions are welcome. I can add more register stage to this but that can affect the performance. I am not su...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Have you tried separating your assignment from the declaration? Altera may not be supporting all the system verilog style assignments for synthesis.

like this,

wire wTag;

assign wTag = RxStreamData0[72] & ~ReqInFifoDataIn[72];