why qsys use type "logic" for inout? inouts are nets by definition, not variable.

Hi, In SystemVerilog RTL design, 'logic' declare can only used in: 1. All point-to-point nets. If you specifically need a multi-driver net, then use one of the traditional net types like wire 2. All variables (logic driven by always blocks) 3. All input ports 4. All output ports Multiple assignments, or mixing continuous and procedural assignments, to a SystemVerilog variable is an error, which means you will most likely see compile error. Mixing and multiple assignments is only allowed for a net. Since 'inout' is a multiple-driven net, hence you will need to declare it as 'wire'. You may refer to the link below for more information: https://www.verilogpro.com/verilog-reg-verilog-wire-systemverilog-logic/ Thanks