Forum Discussion

JJohn10's avatar
JJohn10
Icon for New Contributor rankNew Contributor
7 years ago

Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow?

Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow? There is no a P&R stage (as in ASIC flow)... Is it not enough just to check the logs and reports of the synthesis tools in order to...
Tricky's avatar
Tricky
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I have never done any LEC in FPGA, and I dont know anyone who has.

Like I said, it has all been RTL simulation + good timing specs then program the chip and see if it works.