Forum Discussion

Mirei's avatar
Mirei
Icon for New Contributor rankNew Contributor
7 years ago

Why is my block "synthesized away"?

I'm an FPGA newbie scratching the surface of all this stuff. Could someone please have a look at the attached project? I had it successfully running with "spi_slave.vhd" as top level entity and th...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

There were few inputs/outputs that were unconnected. I've corrected them and also added few others.. Take a look at the Qar file and modify accordingly. Now, the PLL and other registers are not optimized away.