Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Why I cannot see the my state machine in the statemachine viewer?

Hi all, I'm new in FPGA and Quartus EDA tools. I tried to design a simple state machine with the verilog code. It can be simulated successfully, but I don't think it was actually recognized as a S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The state-machine only has two states and synthesis reduced it to a single register. You can see this single register in the RTL viewer (will have 'state' in its reference)

Try adding a third state, it will then show up as a state machine.