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Altera_Forum's avatar
Altera_Forum
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8 years ago

Why does the same path have different timing in TimeQuest?

Hello! I'm trying to constraint a source-synchronous output on my FPGA but I'm getting some timing numbers I can't quite understand (I feel they should be different). I've read Rysc's pdfs on bo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

That makes sense, now that you mention it I remember you wrote about it in your TimeQuest guide (about common clock path pessimism). I just hadn't yet fully understood this was what you meant.

The ccpp removal is in the left screenshot, line 35, I just didn't include that column because I thought what I was seeing had something to do with the path and on all the other lines it just included net names so I figured it wasn't relevant.

Thank you for your time! =)