Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

I'm looking at the Technology Map Viewer (Post-Fitting) option under Fitter (Place & Route). I found no such option 'Enable Input/Output register assignment' in the Assignment editor (from the long list of items presented). Only 'Fast Ouput register' which tells Quartus (according to my reading) to put the register in an I/O cell. What version of Quartus are you using? I'm using 18.1 Standard edition.