Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

Did you take a look at the Post-Fit View? This view shows how its implemented exactly on the device post fitting stage. From the code you sent, I do not see those xtra LCELL block in the Post-Fit view. Plus I used the Enable Fast Input/Output register assignment in the Assignment editor for the therm_reg register.