Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

I did not mean to set optimize hold timing to the default. I meant to set it to off so that no additional routing (or apparently) LEs get added into the path.

And when is a clock not a clock? What are you trying to accomplish?

#iwork4intel