Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

Do you have tight hold timing? If not, then you would not want to use optimize hold timing because that adds additional routing to paths (don't recall if that adds buffers though).

Have you checked the compilation report? Perhaps there's something in there or the compilation messages that explains why these buffers are getting added.

#iwork4intel