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Bosenraum's avatar
Bosenraum
Icon for New Contributor rankNew Contributor
7 years ago

Why does Qsys stop responding when generating DDR3 external memory interface?

I am trying to generate a design that is using the DDR3 SDRAM Controller with UniPHY IP core and during the Qsys HDL generation the generate window will hang rendering Qsys unusable. I am using Quart...
Bosenraum's avatar
Bosenraum
Icon for New Contributor rankNew Contributor
7 years ago

I have managed to workaround this issue by fully re-imaging my Windows 10 machine. I still have no idea what the root cause of this issue is but at least i can continue working now.

  • billmax's avatar
    billmax
    Icon for New Contributor rankNew Contributor
    5 years ago

    I'm seeing the same error with DDR3 uniphy_mcc generation, across multiple versions of Quartus from 15.1 to 20.1 (pre- and post- the switch to wsl). I don't know what has changed on this machine since it was working... below is an example but I get it on any generation of any DDR3 IP.

    Info: m0: "emif_0" instantiated altera_mem_if_ddr3_afi_mux "m0"
    Error: s0: Error during execution of "{E:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
    Error: s0: Execution of command "{E:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
    Error: s0: /mnt/e/intelfpga/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../lreso_rbo_bw_ddr3_system_0_bw_ddr3_mst_emif_0_s0_AC_ROM.hex -inst_rom ../lreso_rbo_bw_ddr3_system_0_bw_ddr3_mst_emif_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0110001110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0110101110000 -DAC_ROM_MR1=0000001000110 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001001011000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0110001101001 -DAC_ROM_MR0_DLL_RESET_MIRR=0110011101000 -DAC_ROM_MR1_MIRR=0000000100110 -DAC_ROM_MR2_MIRR=0001000111000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=1 -DHALF_RATE=0 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
    Error: s0: UniPHY Sequencer Microcode Compiler
    Error: s0: Copyright (C) 2020 Intel Corporation. All rights reserved.
    Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
    Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
    Error: s0: Info: Writing ../lreso_rbo_bw_ddr3_system_0_bw_ddr3_mst_emif_0_s0_AC_ROM.hex ...
    Error: s0: Info: Writing ../lreso_rbo_bw_ddr3_system_0_bw_ddr3_mst_emif_0_s0_inst_ROM.hex ...
    Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
    Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
    Error: s0: Info: Writing sequencer/sequencer_auto.h ...
    Error: s0: Info: Writing sequencer/sequencer_auto.h ...
    Error: s0: Info: Writing ../sequencer_auto_h.sv ...
    Error: s0: Info: Microcode compilation successful

    • MADesigner's avatar
      MADesigner
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Did you ever solve this issue. I am having the exact same problem.