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*What* makes the ddr 3 controller so special that it requires the qsys to be the top level design component?
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This is not correct. I never use Qsys as the top-level module.
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I like to work from a blank slate, adding what I need at places where I think they are needed, with a hierarchy that I think is appropriate
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Yep, me too. With that in mind, take a look at this DE0-nano SDRAM project and this BeMicro-CV DDR3 project. They demonstrate how you can create everything from scratch via Tcl scripts and source code.
http://www.alteraforum.com/forum/showthread.php?t=45927 (see Post#2 attachment)
http://www.alteraforum.com/forum/showthread.php?t=43992 (see Post#5 attachment)
Cheers,
Dave
Honored Contributor
