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Altera_Forum's avatar
Altera_Forum
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7 years ago

why different simulation outputs modelsim and simulation wave editor for ring osc..

Hello to everyone. I apologize for disturbing you. I am trying to modeling ring oscillator in FPGA. You can see my design details in attached photo files. At first modeled it schemat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

Yes, In simulation result we can see the difference.

This is because of the conversion(.bdf to .vhd/.v) which we are doing.

The conversion is adding some extra delay/logic which can be seen in RTL viewer because of which we are getting the different results.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)