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Altera_Forum
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9 years ago

Why a second process requires a signal "conditional" statement in order to work

Hi guys. I'm working on an exercise for an undergraduate class, where I want the students to learn about different "processes" running in a single VHDL architecture. The goal is show them, it i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Modelsim will probably do the job you expect but synthesis tool ignores sensitivity list though wants it there. It is tool issue, nothing else. Hence from synthesis perspective presence of inc in second process is unrelated to q:= q+1 which will be seen as create comb feedback