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Altera_Forum
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9 years ago

Why a second process requires a signal "conditional" statement in order to work

Hi guys. I'm working on an exercise for an undergraduate class, where I want the students to learn about different "processes" running in a single VHDL architecture. The goal is show them, it i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Not taken @Tricky, it is always time to learn more..

Nevertheless, @kaz got the synthesised behavior.

But "inc" is present in the second process "out1 <=inc;", why the signal is not seen without the red lines?