Why a second process requires a signal "conditional" statement in order to work

I Dont want to sound offensive, but as a teacher, you have written VHDL in a very bad style. Please Please read up on VHDL and good practice in regards to coding templates as you will be be passing on whatever you write. Your clocked process does not create a register - it tranditionally creates a transparent latch (although new versions of the tool WILL create a register, but I would not rely on this)

The problem here is the way synthesis handles VHDL compared to the simulator handles VHDL, and the poor choice of VHDL used to produce the counter.

As a rule, you should treat sensitivity lists as non-existent in the synthesis engine. So while it may work perfectly fine without the if statement in simulation, the synthesised hardware just makes Q into an adder that attempts to feedback itself and increment in 0 time. With the inc there, you just made a latch - which is very poor design pratice in FPGAs as they are prone timing issues (and they dont exist on an FPGA and have to be emulated).

Using good practice, I would make inc the clock enable of a counter. I would also steer clear of using variables at all in beginner classes - there is NOTHING in VHDL you can do in synthesisable VHDL that requires a variable and cannot be done using signals. If they have any programming knowledge, variables are going to confuse them. Please stick to signals only.

There is also another problem - integers do not roll over in VHDL - but the synthesised hardware will - another simulation/synthesis missmatch. The fix here is to use the unsigned type which does roll over as expected, and is part of the VHDL standard (Also - please never use std_logic_arith or std_logic_signed/unsigned packages, as these are NOT part of the VHDL standard):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;  -- for unsigned type
Qc : out unsigned(3 downto 0);  -- 4 bit output 0 to 15
....
signal qc_i : unsigned(3 downto 0) := x"0";
process(clk)
begin
  if rising_edge(clk) then
    if inc = '1' then
      qc_i <= qc_i + 1;
    end if;
  end if;
end process;
Qc <= qc_i;

Ill leave you to fix the "1st" process