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No. An assignment inside the clock edge sensitive block implies a delay of one clock cycle, the shown construct creates just a wire respectively a copy of sr(6). Of course there other ways to achieve the same.
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ser_out <= sr(6); can go after the end if; (associated rising_edge(clk)) before end process; and not infer a register.
was the OP interested in this case? both should have the same result, but i'm not sure if one is better than the other. its clear the way FvM's example that the assignment is not in the process, just simply a wire not a register etc.
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