Forum Discussion
Altera_Forum
Honored Contributor
16 years agoOnly Modelsim DE supports proper SystemVerilog assertions. The problem is that many proprietary "assertion based verification" tools and verilog add-ons have been proposed by HDL vendors (i.e. PSL, sugar... etc). And now finally after many years they finally decided to standardize them and introduce them to the standard language, so you need to give modelsim some time to implement them. Not good for us SystemVerilog users I know :(