Which clock should I use for JTAG UART Module?

The Avalon-MM clock crossing bridge will mostly help achieve better performance. I'm not sure about it's consequences on signal timing.

Is the clock crossing bridge has FIFOs it can pipeline several requests between the two domains, resulting in better performance with masters that can do pipelining (mostly DMAs, and the CPU if it has caches). If you connect two components from different clock domains without the clock crossing bridge, QSys will generate much simpler clock crossing logic that will work but that can only handle one transaction at a time.