Where is the "Create VHDL instantiation template file for current files"?

Hi there,

I have a question about quartus II.

If I want to generate VHDL substantiation files by right click the .vhd file.

However, I only see the "verilog instantiation for current file" and "VHDL component declareation for the current file" in the label?

That is confusing.

Can you tell me how to create vhdl instantiation file?

Thanks.