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Altera_Forum's avatar
Altera_Forum
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11 years ago

Where is "EMIF IP byte enable option"?

Hi! I have a SoC FPGA board (DE1 SoC) and did a setup using AVALON MM reading and writing 8bit from the HPS (Linux), now I wanted to extend the bit width to 128bit. When I generated the component set...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The knowledge base article you linked to is talking about a specific problem with using the Altera DDR3 controller under some conditions.

The actual error message you posted sounds more like a problem with the custom IP that you have added in your system. If this is true, then this is an issue you will need to resolve in your _hw.tcl and .v by adding support for byteenable's.