Forum Discussion
New Contributorwhen using quartus 18. Why I can't put all my global `define statement in a seperate file and use it as we do in old-version quartus?
Hmm.. okay, let me clear the air regarding this.
First the 3 versions are different in the way they handle include files.
Lite / Std : We need to add the include files (be it with .v / .inc / .svh extension ) to the project and designate the top-level file. Then just compile. The tool automatically includes the defines / parameters file during compilation and it goes through.
Pro version : This version is modeled just like the industry ASIC compilers/synthesis tools. Here, even after we include the files into the file list, we still need to manually mention this include file in the design file using the `include <> compiler directive. This instructs the compiler to search for this file and include it during the compile process.
@Kevin Hsing .. I suggest you just add the `include "define.v" statement to the start of your design file. Make sure the path to the file is correct. If the define.v file is in the same folder as the source file, then its okay as is.. `include "deinfe.v"
This will include the file during compilation and you should not see those errors/warning.
New Contributor@Abe
Thank you for your feedback.
I build a project and synthesis it using 18.0,it did works .
But I am using quartus18.0 pro(I'm evaluating stratix10 for my project, only 18.0pro support stratix10), same project failed. the tool gave me a critical warning, saying my macro not defined.
It seems Quartus18.0 pro and quartus18/quartus18-lite are totally different, their behavior when parsing rtl source code are quite different.
I tried the method your link provides,but it didn't work for me.
As I mentioned above, The problem only exist in quartus18-pro. quartus18/quartus18-lite works fine.
I enclose the source code and makefile for my project below:
//define.v
`ifndef MY_DEFINE
`define MY_DEFINE
`define DW 7
`endif//mk_fpga.v
module mk_fpga(
input sys_clk,
input [`DW-1:0] datia,
input [`DW-1:0] datib,
output [`DW*2-1:0] dato
);
assign dato = datia*datib;
endmodule#mk_fpga.tcl
# Load Quartus II Tcl Project package
package require ::quartus::project
load_package flow
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "mk_fpga"]} {
puts "Project mk_fpga is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists mk_fpga]} {
project_open -revision [lindex $argv 0] mk_fpga
} else {
project_new -revision [lindex $argv 0] mk_fpga
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name VERILOG_FILE define.v
set_global_assignment -name VERILOG_FILE mk_fpga.v
}
# Commit assignments
export_assignments
puts "++++++ assignment complete"
execute_flow -compile
# Close project
if {$need_to_close_project} {
project_close
} #makefile
PRJ_NAME=mk_fpga
DATE=`date +%y%m%d_%H%M`
#quartus18.0 pro
q18p:
/home/opt/intelFPGA_pro/18.0/quartus/bin/quartus_sh -t $(PRJ_NAME).tcl $(PRJ_NAME)
#quartus18.0
q18s:
/home/opt/intelFPGA/18.0/quartus/bin/quartus_sh -t $(PRJ_NAME).tcl $(PRJ_NAME)
