Forum Discussion
New Contributorwhen using quartus 18. Why I can't put all my global `define statement in a seperate file and use it as we do in old-version quartus?
Hmm.. okay, let me clear the air regarding this.
First the 3 versions are different in the way they handle include files.
Lite / Std : We need to add the include files (be it with .v / .inc / .svh extension ) to the project and designate the top-level file. Then just compile. The tool automatically includes the defines / parameters file during compilation and it goes through.
Pro version : This version is modeled just like the industry ASIC compilers/synthesis tools. Here, even after we include the files into the file list, we still need to manually mention this include file in the design file using the `include <> compiler directive. This instructs the compiler to search for this file and include it during the compile process.
@Kevin Hsing .. I suggest you just add the `include "define.v" statement to the start of your design file. Make sure the path to the file is correct. If the define.v file is in the same folder as the source file, then its okay as is.. `include "deinfe.v"
This will include the file during compilation and you should not see those errors/warning.
Frequent ContributorI've done this and it works in Quartus 18 Lite version. I've created a simple RAM design with a defines.v file that has the `defines in it. The tool picks up the defines and processes it accordingly.
// Single port RAM with single read/write address
module single_port_ram
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
`ifdef RTL
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
`else
ram_1port ram_1port_inst (
.address ( addr ),
.clock ( clk ),
.data ( data ),
.wren ( we ),
.q ( q )
);
`endif
endmoduleThis is the design file - single_port_ram.v and below is the defines.v file
`ifndef RTL
`define RTL
`endifAs you can see in the screenshot below, the compile goes through. I've done it for both with the RTL defined as well as without and get the intended results. I did mention the design file as Top-level entity via the Files tab and then just proceeded with the compile.
