when I generated PLL ip before, a file name _inst.v was generated, so I can copy the example to my script. but the new one in quartus 17/18, the file seems missing. where can I find the example file?

Hi, Vikas.

when I use Quartus17 to open the PLL file( my is base_clock.v) the megawizad was appear and then the "Create Verilog instantiation Template files for current file" is grey out.

then I tried Quartus18, the file was opened at editor window and as you told, everything is fine.

Thank you very much.