What's Wrong with This SV Code Involving Interfaces?

My bad... all the elements of a struct must share the same type of assignment. My combination of continuous and procedural assignments above is what caused the initial state confusion. Structs aren't necessary for what I was trying to do, anyway. Here's a version that works in ModelSim and builds in Quartus:

interface my_interface;
    logic      some_byte;
    logic           increment_enable;   //This is an input from another module
endinterface
module fpga_test(
    input   wire                clk,
    my_interface                ports 
);
    //Create arrays used to work around the issue of not being able to access elements of a port array in loops
    logic increment_enables ;
    logic  some_bytes ;
    
    //Use generated assignments to make the local arrays proxies for the port array elements.
    genvar n;
    generate
        for(n=0; n<4; n++) begin: port_assignments
            assign ports.some_byte = some_bytes;
            assign increment_enables = ports.increment_enable;
        end
    endgenerate
    
    initial begin
        for(int n=0; n<4; n++) some_bytes = '1;
    end
    
    function increment_now; //Check if any increment_enable lines are high
        automatic logic result = 0;
        for(int n=0; n<4; n++) result = result | increment_enables;
        return result;
    endfunction
    
    function  get_increment_index; //Get the index of the lowest active increment_enable
        automatic logic  result = '0;
        for(int n=0; n<4; n++) begin
            if(increment_enables) begin
                result = n;
                break;
            end
        end
        return result;
    endfunction
    
    always_ff @(posedge clk) begin
        //Check if any of the increment_enable lines are high. If one or more is high, only act based on the lowest index.
        if(increment_now) some_bytes <= some_bytes + 1'd1;
    end
endmodule