What's Wrong with This SV Code Involving Interfaces?

Thank you for the clarification. That is annoying, because in this case there are no parameters that could lead to the instances being different. It’s too bad there’s no exception for a case like this where every element of the array is identical.

Building from your comment, I wondered what would happen if I inserted a struct between the port array and the rest of the code. I used a generate loop to link the port array with the struct array. Then I just updated my loops to reference the struct array instead of the port array.

interface my_interface;
    logic      some_byte;
    logic           increment_enable;   //This is an input from another module
endinterface
typedef struct {
    logic      some_byte;
    logic           increment_enable;
} my_struct;
module fpga_test(
    input   wire                clk,
    my_interface                ports 
);
    //Create a structure used to work around the issue of not being able to access elements of a port array in loops
    my_struct ports_cheating ; 
    
    //Use generated assignments to make the structure array a proxy for the port array.
    genvar n;
    generate
        for(n=0; n<4; n++) begin: port_assignments
            assign ports.some_byte = ports_cheating.some_byte;
            assign ports_cheating.increment_enable = ports.increment_enable;
        end
    endgenerate
    
    initial begin
        for(int n=0; n<4; n++) ports_cheating.some_byte = '1;
    end
    
    always_ff @(posedge clk) begin
        //Check if any of the increment_enable lines are high. If one or more is high, only act based on the lowest index.
        if(increment_now) ports_cheating.some_byte <= ports_cheating.some_byte + 1'd1;
    end
    
    function increment_now; //Check if any increment_enable lines are high
        logic result = 0;
        for(int n=0; n<4; n++) result = result | ports_cheating.increment_enable;
        return result;
    endfunction
    
    function  get_increment_index; //Get the index of the lowest active increment_enable
        logic  result = '0;
        for(int n=0; n<4; n++) begin
            if(ports_cheating.increment_enable) begin
                result = n;
                break;
            end
        end
        return result;
    endfunction
endmodule

That builds! It has a couple issues, though. It doesn't run in the Quartus simulator (it looks like ModelSim says there's an error in the .do file that Quartus is generating). I'll try it in a real testbench next. It also has a worrisome warning:

"Warning (10855): Verilog HDL warning at fpga_test.sv(27): initial value for variable ports_cheating should be constant"

'1 is clearly a constant value. What is unclear about that? I don't see any inversions happening in the Technology Map Viewer, so it looks like the initial statements are probably being ignored.