What's Wrong with This SV Code Involving Interfaces?

I think I see what you’re saying, but I’m struggling to make it work for what I actually want to do. As far as seeing what you mean, this design builds fine for me in Quartus:

interface my_interface;
    logic      some_byte;
endinterface
module fpga_test(
    input   wire                clk,
    my_interface                ports 
);
    genvar n;
    generate 
        for(n=0; n<4; n++) begin: init_ports
            initial ports.some_byte = '1;
            
            always_ff @(posedge clk) ports.some_byte <= ports.some_byte + 1'd1;
        end
    endgenerate
endmodule

In practice, though, I’m trying to use this in an application where all the ports are sharing a single resource. I need priority so that when multiple ports request the resource, only the lowest index port is given access.

I came up with an example that’s closer to what I want to do. I started by writing it out explicitly. The idea here is that the fpga_test module initializes and increments the some_byte register in each port. Each port has a an increment_enable signal that comes from the outside world. If increment_enable is asserted on any of the ports, I want only the lowest numbered port to increment. That simulates the concept of priority that I’m trying to achieve. This explicit version builds in Quartus:

interface my_interface;
    logic      some_byte;
    logic           increment_enable;   //This is an input from another module
endinterface
module fpga_test(
    input   wire                clk,
    my_interface                ports 
);
    initial begin
        ports.some_byte = '1;
        ports.some_byte = '1;
        ports.some_byte = '1;
        ports.some_byte = '1;
    end
    
    always_ff @(posedge clk) begin
        //Check if any of the increment_enable lines are high. If one or more is high, only act based on the
        //lowest index.
        if(increment_now) ports.some_byte <= ports.some_byte + 1'd1;
    end
    
    function increment_now; //Check if any increment_enable lines are high
        logic result = 0;
        //Written like this so that it's obvious how to make it into a for loop
        result = result | ports.increment_enable;
        result = result | ports.increment_enable;
        result = result | ports.increment_enable;
        result = result | ports.increment_enable;
        return result;
    endfunction
    
    function  get_increment_index; //Get the index of the lowest active increment_enable
        logic  result = '0;
        //Written like this so that it's obvious how to make it into a for loop
        if      (ports.increment_enable) result = 2'd0;
        else if (ports.increment_enable) result = 2'd1;
        else if (ports.increment_enable) result = 2'd2;
        else if (ports.increment_enable) result = 2'd3;
        return result;
    endfunction
endmodule

Can this be made to work with loops so that I can parameterize the number of ports? I get build errors when trying to make almost any of that loop-based. I can't even get the functions alone to build when written as loops.